Do you have the right ‘connection’? October 21, 2009
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There is a lot of conversation these days about the impact of Electronic System Virtualization (ESV) on software development. Isn’t it obvious, that it is much better to develop software earlier, before chips are available? Don’t you agree that looking into the guts a multi-core platform for debugging a tough multi-threading problem is much easier using a Virtual Platform, than to use a board with a JTAG connected debugger? Wouldn’t it be nice if the semiconductor and OEM supply chain use this as their standard way of accelerating their time to market? Isn’t this the only problem that ESV addresses?
Actually this only one problem, albeit a big one, that ESV addresses. It deals typically with the next generation silicon and product, which in most companies is called N+1.
What about the products, that are further out, say N+3? Do you have the software applications that will run on those products in your hand today? No, they will be invented in the next few years. Do you even know the processors that you will be using for N+3? Maybe, but there are no models for those yet. What you do know today is the type of applications that you need to run. You may know the performance profile in terms of traffic that they trigger. You probably know exactly, which interconnect and protocol you will be using, because the interconnect, the backbone of your chip, is typically stable for many generations of platforms that you are developing or will be using.
Getting a precise idea, what your interconnect will deliver for the myriad of use cases and applications, that you need to support, is critical for making your design decision for N+3. The right ‘connection’ with the right bandwidth and priority management between your processors and the internal/external memory systems determines, if your N+3 chip or end product is competitive or not.
If you are a development engineer at an OEM or semiconductor company, this is what you care about.
However, it is even more critical that your company cares about a ‘connection’ at a business level. If you are the SmartPhone OEM trying to stay ahead of the pack or beating #1, you need to specify the most advanced silicon platform that will deliver on that goal. If you are a semiconductor company, that has a socket in N+1, you want to maintain that socket for N+3 or push your competitor out of it.
If you are the OEM, how do you communicate to your bidders, what they need to deliver? If you are the semiconductor supplier, how do you credibly pitch, what you can do vs. your competitor? The risks for miscommunication and missing the performance are high. What if you had an ESV solution, that serves as the specification that you can rely on for N+3? Do you want to have a ‘connection’ between you as an OEM and you as a semi based on industry leading interconnect IP, protocols and ESV solutions for architecture design?
Missing the ‘connection’? Talk to ARM and CoWare.
How will you deploy Electronic System Virtualization? July 30, 2009
Posted by marcseru in Uncategorized.Tags: architecture, deployment, Electronic system, software, virtualization
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Today the problem for companies developing electronic systems is not anymore the existence of the right technology, but rather how will I deploy it. Electronic System Virtualization must cover areas such as processor design, system architecture, oftware development, go-to-market enablement, configuration, etc. The virtualization of the electronic system must start from the specification all the way to the deployment of the system itself independently of the system being a core, an SoC, a board, a device or a network of devices.
The use of electronic system virtualization is proven to deliver the value. Many companies are now presenting their results and the significant benefit they are getting. However none of these companies have considered a single use case for virtual platforms for example. They have derived results from using virtual platform as an infrastructure across several of the product life cycle tasks.
The implication of this reality is that the deployment of Electronic System Virtualization technologies will require individuals and organizations driving their deployment. It will require executive support, it will require the willingness to introduce changes.
The drivers behind this change will be the leaders of tomorrow.
Virtual Platform Workshop at DAC July 29, 2009
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Qualcomm reporting on the opportunities and challenges of Virtual Platforms for their system designs. QC has been highlighting the productivity gain they get from Virtual Platforms for Software Development, Architecture Definition, Hardware Development and Early Customer Success. Qualcomm is following an incremental Virtual Platform creation approach to incrementally enable software development and get value out of VPs as early as possible. QC has reported a significant quality gain because they are able to develop the tests upfront and do not need to wait until the HW is available for the test development. VPs help QC to improve the coverage of their testing using complex software use-caes. VPs have enabled QC to create tests that they could not create before. Challenges remain on the Virtual Platform enablement side. For QC it was key to choose a standards-based modeling language and TLM to ensure interoperability between models. The driver to select a tool and/or language is its ability to create virtual platform models that are fast, at a higher level of abstraction, are interoperable, and that can be created in an easy way. QC reported that it is key for them that their engineers are enabled to carry out the modeling. It is of significant importance that a wider set of engineers/IP architects are enabled to create models with the above mentioned characteristics.
System Prototypes: Virtual, Hardware or Hybrid? July 29, 2009
Posted by systemleveldesign in Uncategorized.Tags: analysis, debug, Electronic system, software, virtual platform, virtualization
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The Tuesday’s panel “System Prototypes: Virtual, Hardware or Hybrid” at DAC was well attended with an active and exciting discussion among the panelists and the audience. Panelists came from Amicus Wireless, Qualcomm, LSI, Synopsys, ST-Ericsson and CoWare. There was a consensus that there is no on-size-fits all solution for prototyping. Different design tasks such as system level architecture definition, software prototyping and bring up and implementation prototyping have different requirements on the prototyping solution. Qualcomm and ST-Ericsson have reported about their successful adoption of virtual prototyping using Virtual Platforms for early software development. Both reported that Virtual Platforms has significantly smoothed their software bring-up step-function that they typically had without Virtual Platforms and when the hardware became available late in the design. Questions have been raised about the accuracy of Virtual Platforms. Here, the panelists where in agreement that a Virtual Platform does need to provide the accuracy required for the different design tasks such as being just functional accurate for software development. I have been reporting a trend that we see at our Electronic System Virtualization solution users moving away from spreadsheets for the architecture definition. This was hitting a question from the audience how Virtual Platforms can be used for HW/SW partitioning. System level architecture prototyping is done using non-functional workload models characterizing traffic scenarios for application/task mapping as well as interconnect and memory subsystem optimization. This way the dynamics of a system can be captured which is not possible using static spreadsheets. Other questions were about using Virtual Platforms after silicon is out. Here, the Google Android Emulator was mentioned as a perfect example how Virtual Platforms deliver value to even the application software developers by having access to a fully virtualized environment including GPS, Internet, Accelerometer to develop disruptive applications. People in the audience where also reporting about the trouble they face when trying to bring up systems on an FPGA, it simply does not fit for many cases. FPGAs are used for block level implementation prototyping but cannot provide a full environment. It was an exciting panel and it has clearly shown the increasing demand and adoption of Virtual Platforms in the industry.
A rant: Will the agent of change for SW stand up? July 29, 2009
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How many time have I heard now that software is the growing problem, that software is the savior for the traditional EDA companies, that the software teams are out growing the hardware team, yet the software tools budget are not, …
This week design automation conference is no different; you can hear it from the CEO of the EDA companies to their soldiers, from the executive of semiconductor companies to their soldiers, from the analyst to the press, to even the taxi driver in San Francisco. Software is the problem; we need to do something about it!
But yet when it comes to doing something very little of these players are effectively executing on it. Everything is very much about RTL, optimization of the hardware, etc. The true software solutions are few. The first thing we hear from customers is “yes it is about the software, but what about my hardware problem”. The second is from the companies (trying to protect their legacy) “yes, software is the problem, but let me explain to you how what I have today solves the problem”
Well let’s be realistic, if what exists today from these companies and what is being used by the engineers was solving the problem, then there would be no problem!
Addressing the software problem requires the willingness to change. To change the development process, to retool, to be willing to say I want to invest in these new technologies, to be willing to look at the product life cycle management, to stand up and say “Yes there is a software problem and I will not wait for the storm to pass before I fix it”, “Yes there is a software problem and I will lead my organization to make this difficult but necessary change”.
Are you this engineer, this manager, this executive that will say yes and drive the change? If not get out of the way, the wave is coming anyway.
NASCUG Does It Again at DAC July 28, 2009
Posted by systemleveldesign in Uncategorized.Tags: architecture design, electronic, system, SystemC, TLM, virtual platform, virtualization
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The North America SystemC User Group (NASCUG) once again held it’s popular SystemC user group meeting at DAC. Attendance was good, with over 100 people attending to hear the OSCI update, education on SystemC standards, and technical papers from users on the application of SystemC, and to participate in an open Town Hall meeting style discussion.
Interestingly, many of the attendees were attending NASCUG for the first time. According to the innovative live survey “clicker” response system, 43% were first time attendees. That said, the majority of the attendees considered themselves intermediate, advanced, or power users of SystemC. Before diving into the papers, OSCI announced progress in the TLM WG, AMS WG, and Synthesis WG activities (read more at www.systemc.org) and gave updates on all WG activities, including the new Configuration, Control, and Inspection (CCI) WG.
Technical presentations covered modeling, software development, architecture design, and verification. For the complete agenda and access to the presentations, visit www.nascug.org.
Proven! ST-Ericsson Virtual Platform usage presentation at DAC 2009 July 28, 2009
Posted by marcseru in Uncategorized.Tags: ARM, cortex, coware, Electronic System Virtualization, ESV, FPGA, virtual platform
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I listened today to the presentation from Olivier Mielo, a software engineer from ST-Ericsson. It was a very exciting presentation on why virtual platform will be the way to move forward to address the curretn challenges of software development.
In his presentation Olivier talked about the use of a SystemC virtual platform to develop and validate a UMTS layer1 protocol stack. Here are some of the great points that he made.
He first explained the design challenges which included:
- Needing a “Software centric” approach to address multiple use cases
- Develop and validate layer 1 (layer 2/3 ) software covering HSXPA protocol while keeping up and running on the new architecture existing layer 1 UTMS R.99 software
- Reduce the time to get the “final” solution and be confronted to test approval in front of base station as soon as possible as well as be in time for the mass production with customers
He then explained why traditional methods such as FPGA protoypes or stand alone proprietary simulation would not work. Here are his points on FPGA:
- Need a new net list each time the architecture is changing
- Not so easy to spread complex design over many FPGA
- Allows partial visibility on the system through JTAG
- Difficult to debug multi-cores software without breaking real time conditions
They decided to deploy virtual platforms using CoWare technologies and expertise. After explaining their deployment and use, the following conclusion were reached:
- Virtual Platform was available to start software development within a month
- Software development was shorten and completed before RTL
- Early system integration and validation was done (They had a full Virtual Platform test bench with the base station tester from ANITE integrated)
- The powerful debug support made their work much easier and reduced the project risks.
You can listen to his presentation by visiting the CoWare booth #3665 at DAC in San Francisco. There will be replays during the rest of the week.
Big Crowd for CoWare ESV DAC Exhibitor Forum Session July 28, 2009
Posted by systemleveldesign in LTE, system design.Tags: DAC 09, Design Automation Conference, Electronic System Virtualization, ESV
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Presenting at the first exhibitor forum session at DAC, during some difficult economic times, is always somewhat of a risk. It wasn’t clear how big an audience we should expect. Standing in front of the exhibitor forum seating area, I was waiting with my co-presenters without high hopes. The first 5 people started to get seated 20 minutes before the presentation. And eventually attendees filled the seats … I shouldn’t have worried. Over 100 persons attended our presentation on Addressing the Design Challenges of ARM-Based LTE Mobile Phone Designs Using System Virtualization. Together, with IP model partners ARM, Ltd. and Carbon Design Systems, CoWare explained how CoWare Electronic System Virtualization solutions address the design challenges that hardware and software engineers working on LTE mobile phone designs are facing. Based on the questions from the audience, it is clear that standards like SystemC are very important and that the complexity of their designs demand a fast and flexible solution for multi-core designs.
These items are exactly some of the key strengths of CoWare Electronic System Virtualization solutions. As recent customer success stories prove, not only has CoWare been consistently leading the industry with standards-based ESV solutions, customers are choosing CoWare ESV solutions for their complex multi-core designs. Since this type of design is becoming the de facto standard for today’s electronic devices, virtualization needs will only grow.
Looking back at the audience for the electronic system virtualization exhibitor forum session, interest in system virtualization is already growing and people are more than ever looking at CoWare to help pull in design time, lower costs and enable the supply chain. It is promising to be an interesting DAC.
